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general description the ds3908 contains two nonvolatile digital poten- tiometers with programmable-gain amplifiers buffering the wiper outputs. the potentiometer position and amplifier gain are controlled through an i 2 c*-compati- ble serial bus. the ds3908 operates in both 3.3v and 5v systems and features a write-protect pin that locks the position of the potentiometers and gain registers. up to eight ds3908s can be placed on a single i 2 c bus. applications pin-diode biasing power-supply calibration cell phones and pdas portable electronics features two 64-position linear taper potentiometers integral wiper buffering amplifiers with selectable gains of 1v/v, 2v/v, or 4v/v 100k ? potentiometer end-to-end resistance low potentiometer temperature coefficient nonvolatile wiper and gain storage i 2 c-compatible interface write-protect pin prevents accidental field reprogramming 3v to 5.5v supply voltage range -40? to +85? operating temperature range 14-pin tdfn package ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs ______________________________________________ maxim integrated products 1 tdfn (3mm x 3mm) top view 2 4 5 13 11 10 h1 l1 h0 scl a1 a2 1 + 14 v cc sda 3 12 v1 a0 6 9 v0 wp 7 8 l0 gnd ds3908 pin configuration pot0 h0 v0 l0 h1 v1 l1 i 2 c interface sda scl a0 a1 a2 wp voltage reference nv adjustable reference voltage nv adjustable reference voltage v cc ds3908 pga0 pot1 pga1 typical operating circuit rev 0; 4/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes lead-free package. ordering information part temp range pin-package ds3908n+ -40? to +85? 14 tdfn i 2 c is a trademark of philips corp. purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc , sda, and scl relative to gnd .....-0.5v to +6.0v voltage on a0, a1, a2, l0, l1, h0, h1, and wp relative to gnd................-0.5v to (v cc + 0.5v) (not to exceed +6.0v) operating temperature range ...........................-40? to +85? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature ............refer to j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) +3.0 +5.5 v input logic 1 (scl, sda, a0, a1, a2, wp) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (scl, sda, a0, a1, a2, wp) v il -0.3 0.3 x v cc v potentiometer voltage (l0, l1, h0, h1) v cc = +3.0v to +5.5v -0.3 v cc + 0.3v v dc electrical characteristics (v cc = +3.0v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units input leakage i l -1 +1 a standby supply current i stby v cc = 5.5v (note 2) 2 ma v ol1 3ma sink current 0 0.4 low-level output voltage (sda) v ol2 6ma sink current 0 0.6 v i/o capacitance c i/o 10 pf wp internal pullup resistance r wp 40 65 100 k ? analog potentiometer characteristics (v cc = +3.0v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units end-to-end resistance +25 c 79 100 121 k ? absolute linearity inl (notes 3, 4) -0.6 +0.6 lsb relative linearity dnl (notes 4, 5) -0.25 +0.25 lsb end-to-end temperature coefficient 50 ppm/ c
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs _____________________________________________________________________ 3 ac electrical characteristics (v cc = +3.0v to +5.5v, t a = -40 c to +85 c.) (see figure 2.) parameter symbol conditions min typ max units scl clock frequency f scl (note 6) 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd:sta 0.6 s low period of scl t low 1.3 s high period of scl t high 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s sda and scl rise time t r (note 7) 20 + 0.1c b 300 ns sda and scl fall time t f (note 7) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s sda and scl capacitance c b (note 7) 400 pf eeprom write time t w (note 8) 10 17 ms startup time t st v cc = 3.0v 40 s programmable-gain amplifier characteristics (v cc = +3.0v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units common-mode input voltage cmv in 0 v cc - 1.5 v r l 2k ? , g = 1v/v 0.975 1 1.025 r l 2k ? , g = 2v/v 1.925 2 2.05 gain g r l 2k ? , g = 4v/v 3.850 4 4.10 v/v output voltage range v out r l = 2k ? , -1ma < i out < 1ma 0.3 v cc - 0.3 v power-supply rejection ratio psrr 60 90 db output source current i out:source v out = 0v, hx = lx = 1v -15 ma output sink current i out:sink v out = 1v, hx = lx = 0v 15 ma unity-gain frequency f t gain = 1v/v, position 3fh 3.5 mhz amplifier capacitive loading c l 100 pf input offset voltage v os -9 +9 mv load regulation -1ma < i out < 1ma 800 2200 v/ma output-voltage slew rate r l = 10k ? , c l = 10pf 270 840 v/ms
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs 4 _____________________________________________________________________ nonvolatile memory characteristics (v cc = +3.0v to +5.5v.) parameter symbol conditions min max units eeprom write cycles at +70 c 50,000 note 1: all voltages are referenced to ground. note 2: i stby specified assuming control pins are connected as follows: wp must be disconnected or connected high. h terminal connected to v cc , l terminal connected to gnd, potentiometer position 1dh, pga is at 2v/v, a0 to a2 connected to v cc , sda and scl connected to v cc , with no load. note 3: absolute linearity is used to measure expected wiper voltage as determined by wiper position in a voltage-divider configuration. note 4: this specification only refers to the potentiometers, and does not include the gain and offset error due to the pga. note 5: relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions in a voltage- divider configuration. note 6: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c stan- dard-mode timing. note 7: c b total capacitance of one bus line in picofarads, timing referenced to 0.9 x v cc and 0.1 x v cc . note 8: eeprom write begins after a stop condition occurs. 0 0.6 0.4 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 3.0 4.0 3.5 4.5 5.0 5.5 standby supply current vs. supply voltage ds3908 toc01 v cc i stby (ma) hx = v cc , lx = gnd a0 to a2 = v cc sda, scl = v cc pot at 1dh gain = 2v/v no load +85 c +25 c -40 c 0 0.6 0.4 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 10 -15 35 60 85 standby supply current vs. temperature ds3908 toc02 temperature ( c) i stby (ma) 3.3v 5.5v 4.0v 1 10,000 1,000,000 standby supply current vs. scl frequency ds3908 toc03 scl frequency (hz) i stby (ma) 100 1.16400 1.15000 1.15200 1.15400 1.15600 1.15800 1.16200 1.16000 typical operating characteristics (t a = +25 c, unless otherwise noted.) 1.30000 1.10000 1.50000 1.40000 1.60000 1.70000 1.80000 1.90000 1.00000 0 102030405060 output voltage vs. pot setting ds3908 toc04 pot setting (dec) output voltage at vx (ma) gain = 1v/v hx = 1v lx = 0.3v 0.001 0.01 0.1 1 10 100 v ol vs. i out:sink 1 0.1 0.01 0.001 10 ds3908 toc05 i out:sink (ma) v ol (v) +85 c +25 c -40 c 0.001 0.01 0.1 1 10 100 v cc - v oh vs. i out:source 1 0.1 0.01 0.001 10 ds3908 toc06 i out:source (ma) v cc - v oh (v) +85 c +25 c -40 c
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs _____________________________________________________________________ 5 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 -40 10 -15 356085 normalized pot end-end resistance vs. temperature ds3908 toc07 temperature ( c) normalized pot end-end resistance ( ? / ? ) v cc = 5v -1.25 -0.10 -0.15 -0.20 -0.05 0 0.05 0.10 0.15 0.20 0.25 0 102030405060 pot inl vs. setting ds3908 toc08 pot0 setting (dec) pot inl (lsb) gain = 1v/v -1.25 -0.10 -0.15 -0.20 -0.05 0 0.05 0.10 0.15 0.20 0.25 0 102030405060 pot dnl vs. setting ds3908 toc09 pot0 setting (dec) pot dnl (lsb) gain = 1v/v -0.5 0.6 -0.2 -0.4 -0.3 0.1 0 -0.1 0.5 0.4 0.3 0.2 0.3 1.5 1.9 0.7 1.1 2.3 2.7 3.1 3.5 typical pga offset vs. common-mode input voltage ds3908 toc10 common-mode input voltage (v) typical pga offset (mv) gain = 1v/v data offset to show 0 at 2v cmv in +85 c +25 c -40 c -0.2 -0.1 -0.15 0.05 0 -0.05 0.2 0.15 0.1 0.25 -40 10 -15 35 60 85 typical pga offset vs. temperature ds3908 toc11 temperature ( c) typical pga offset (mv) cmv in = 0.3v cmv in = 2.0v cmv in = 3.5v pin description tdfn pin name function 1 sda i 2 c serial data. input/output for i 2 c data. 2 scl i 2 c serial clock. input for i 2 c clock. 3, 4, 5 a0, a1, a2 address-select inputs. determines i 2 c address. device address is 1010a 2 a 1 a 0 . (see the i 2 c slave address and address pins section for more details.) 6wp write-protect input. must be grounded to write to the registers. an internal pullup will lock the register values if this pin is not connected. 7 gnd ground terminal 8, 11 l0, l1 potentiometer low terminals. voltages on these pins should remain between gnd and v cc . 9, 12 v0, v1 amplifier outputs 10, 13 h0, h1 potentiometer high terminals. voltages on these pins should remain between gnd and v cc . 14 v cc supply voltage terminal typical operating characteristics (continued) (t a = +25 c, unless otherwise noted.)
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs 6 _____________________________________________________________________ pot0 h0 v0 l0 h1 v1 l1 i 2 c interface sda scl a0 a1 a2 wp gnd v cc ds3908 pga0 pot1 pga1 v cc v cc r wp 1x, 2x, 4x gain f8h f9h fah fbh g1 g0 eeprom 1x, 2x, 4x gain pot0 register pot1 register pot0/1 register functional diagram detailed description the ds3908 contains two nonvolatile digital poten- tiometers with programmable-gain amplifiers buffering the wiper outputs. the potentiometers have 63 equally weighted (linear- taper) resistive elements, for a total of 64 taps. the resistive elements are built using a low-temperature- drift material, and have a typical 100k ? end-to-end resistance. this produces an output that is highly lin- ear, with the highest and lowest taps connected to high (hx) and low (lx) terminals, respectively. the poten- tiometers are independently controlled using an i 2 c- compatible interface. three address pins allow one of eight slave addresses to be selected. the eight slave addresses allow the ds3908 address to be customized for applications with multiple i 2 c devices, and allow up to eight ds3908s to be placed on the same i 2 c bus. the potentiometer positions are saved in eeprom, and are recalled during each power-up to provide non- volatile position settings. once the settings are written, the write-protect pin prevents accidental writes to the potentiometers. the write-protection function is ideal for analog factory calibration because it prevents errant transactions on the i 2 c bus from corrupting the settings of the device. the wp pin contains an internal pullup resistor that must be pulled low to write to the device. the programmable-gain amplifiers can be indepen- dently set to one of three different gains 1v/v, 2v/v, or 4v/v. the amplifiers common-mode input range is from ground to 1.5v below v cc , and the output is rail-to-rail and capable of driving 1ma loads, 300mv from each supply rail. the outputs are stable driving 100pf loads for applications that require output filtering. the addition of the amplifier to buffer the potentiometer wiper offers distinct advantages over standard digital potentiometers. the buffer provides a high-impedance load for the potentiometer and a low-impedance volt- age output. this improves the linearity of the output voltage for systems that load the potentiometer by elim- inating the changes in current through both the poten- tiometer and the wiper impedance. it also allows voltage gain from the potentiometer input to the output. because the amplifiers are integrated into the ds3908, this is done without increasing the footprint of the design or the complexity of the pc board.
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs _____________________________________________________________________ 7 i 2 c slave address and address pins the ds3908 s i 2 c slave address is determined by the state of the a0, a1, and a2 address pins as shown in the pin configuration (see figure 1). address pins con- nected to gnd result in a 0 in the corresponding bit position in the slave address. conversely, address pins connected to v cc result in a 1 in the corresponding bit positions. i 2 c communication is described in detail in the i 2 c serial interface description section. potentiometer control the potentiometers of the ds3908 have 64 taps with 63 resistive elements separating them. thus, the most and least significant wiper positions connect the amplifier to the voltages at the high and low terminals of the poten- tiometer, respectively. the potentiometers of the ds3908 are controlled by communicating with the following registers: *the slave address is determined by address pins a0, a1, and a2. 1 msb slave address* read/write bit lsb 010 a2 a1 a0 r/w figure 1. ds3908 slave address byte table 1. potentiometer registers address potentiometer i 2 c functions number of positions* defaults f8h pot 0 read/write 64 (00h to 3fh) 1fh f9h pot 1 read/write 64 (00h to 3fh) 1fh fah pot 0 and pot 1 write only 64 (00h to 3fh) * the two most significant bits of each potentiometer position register are ignored. writing values greater than 3fh to any of th e potentiometer registers will result in a valid 6-bit position, without regard to the value of the most significant two bits. ex ample: register values c2h, 82h, 42h, and 02h are all potentiometer position 2.
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs 8 _____________________________________________________________________ writes to this register are similar to writes to the poten- tiometer register. a stop condition must follow the write to ensure that the eeprom is modified. a repeated start condition before a stop condition following a write operation will prevent the settings from being stored in eeprom. (see the i 2 c communication section for more details.) write protection the write-protect pin has an internal pullup resistor. to adjust the potentiometers position, this pin must be grounded. this pin can be left floating or connected to v cc to write protect the eeprom memory. all registers can be read when the device is write protected. when writing to the ds3908, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the eeprom (used to make the setting nonvolatile) will be written following the stop condition at the end of the write command. to change the setting without changing the eeprom, ter- minate the write with a repeated start condition before the next stop condition occurs. using a repeated start condition prevents the 20ms (maximum) delay required for the eeprom write cycle to finish. programmable amplifier control the gain of both ds3908 amplifiers is controlled by writing to register address fbh. the most significant nibble of the fbh address controls the pga1 gain, and the least significant nibble controls the pga0 gain. the format of each nibble is shown in the tables below: table 2. programmable amplifier register register format (binary) address pga1 pga0 r* g1 2 g1 1 g1 0 r* g0 2 g0 1 g0 0 fbh bit7 bit0 default value = 11h. *reserved for future use, write to zeros. table 3. programmable amplifier gain codes gx 2 gx 1 gx 0 amplifier gain (v/v) 00x 1 01x 2 1xx 4 x = don t care.
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs _____________________________________________________________________ 9 i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers: master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, and start and stop conditions. slave devices: slave devices send and receive data at the master s request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data trans- fer following the current one. repeated starts are com- monly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see the timing diagram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold-time requirements (see figure 2). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 2) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave dur- ing a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing (figure 2) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is prop- erly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. sda scl t hd:sta t low t high t r t f t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start t buf note: timing is reference to v il(max) and v ih(min) . figure 2. i 2 c timing diagram
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs 10 ____________________________________________________________________ byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minated communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the ds3908 s slave address is determined by the state of the a0, a1, and a2 address pins as shown in figure 1. address pins connected to gnd result in a 0 in the corresponding bit position in the slave address. conversely, address pins connected to v cc result in a 1 in the corresponding bit positions. when the r/ w bit is 0 (such as in a0h), the master is indicating it will write data to the slave. if r/ w = 1, (a1h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the ds3908 will assume the master is communicating with another i 2 c device and ignore the communication until the next start condition is sent. memory address: during an i 2 c write operation to the ds3908, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. the master must read the slave s acknowledgement during all byte write operations. when writing to the ds3908, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the eeprom (used to make the setting nonvolatile) will be written following the stop condition at the end of the write command. to change the setting without changing the eeprom, ter- minate the write with a repeated start condition before the next stop condition occurs. using a repeated start condition prevents the 20ms (maximum) delay required for the eeprom write cycle to finish. if the master continues to write data to the ds3908, without generating a stop condition, then the same reg- ister will be overwritten. acknowledge polling: any time an eeprom byte is written, the ds3908 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte to eeprom. during the eeprom write time, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of this phe- nomenon by repeatedly addressing the ds3908, which allows communication to continue as soon as the ds3908 is ready. the alternative to acknowledge polling is to wait for a maximum period of t w to elapse before attempting to access the device. eeprom write cycles: the ds3908 s eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature. it is capable of handling many additional writes at room temperature. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read oper- ation occurs at the present value of the memory address pointer. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address pointer for reads: a dummy write cycle can be used to force the address pointer to a particular value. to do this, the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. see figure 3 for a read example using the repeated start condition to specify the memory location. applications information power-supply decoupling to achieve the best results when using the ds3908, decouple the power supply with a 0.01f or 0.1f capacitor. use a high-quality, ceramic, surface-mount capacitor if possible. surface-mount components mini- mize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications.
ds3908 dual, 64-position nonvolatile digital potentiometer with buffered outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 ? 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. heaney total error the total error in a reading from the ds3908 can be calculated using the following formula: potvoltage = (potcode / 63) x (v h v l ) + v l error pot = (inl err / 63) x (v h v l ) error offset = gain x v off error gain = potvoltage x gain err total output error = error pot + error offset + error gain where: potcode = potentiometer setting (dec) gain err = amplifier gain deviation from desired (v/v) v off = pga input voltage offset voltage (v) inl err = potentiometer integral non-linearity (lsb) for example, the worst-case error for v h = 2v, v l = 0.5v, pga gain = 2v/v, potcode = 31d (1fh), is given by: potvoltage = 31 / 63 x (2.0v - 0.5v) + 0.5v = 1.238v error pot = (0.6 / 63) x (2.0v - 0.5v) = 0.014v error offset = 2.0v/v x 9mv = 0.018v error gain = potvoltage x gain err = 0.0929v total output error = error pot + error offset + error gain = 0.014v + 0.018v + 0.0929v = 0.125v package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip topology transistor count: 9950 slave address* start start 1 0 1 0 a2 a1 a0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register/memory address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte nonvolatile write -write potentiometer 1 to 00h single byte volatile write -write potentiometer 1 to 00h start stop 10100000 11111 001 a0h f9h repeated start 1 0100000 11111 001 a0h f9h stop pot 0 data example i 2 c transactions (when a0, a1, and a2 are connected to gnd) typical i 2 c write transaction *the slave address is determined by address pins a0, a1, and a2. 00000 000 00000000 single byte read -read potentiometer 0 a) a) b) start stop 101000 00 111 11000 a0h f8h a1h 1010 0001 slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack master nack repeated start figure 3. i 2 c communication examples
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds3908 part number table notes: see the ds3908 quickview data sheet for further information on this product family or download the ds3908 full data sheet (pdf, 224kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds3908n+t&r tdfn;14 pin;118 dwg: 21-0137i (pdf) use pkgcode/variation: t1433+1 * 0c to +70c rohs/lead-free: yes materials analysis DS3908N-001 tdfn;14 pin;118 dwg: 21-0137i (pdf) use pkgcode/variation: t1433-1 * 0c to +70c rohs/lead-free: no DS3908N-001+ tdfn;14 pin;118 dwg: 21-0137i (pdf) use pkgcode/variation: t1433+1 * 0c to +70c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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